1) Field of the Invention
The present invention relates to a memory control device and a move-in buffer control method.
2) Description of the Related Art
Conventionally, the operation speed of a central processor is much faster than the operation speed of a main storage, which raises a problem that when the main storage is referred to, the operation of the central processor must wait for a long time.
In order to solve this problem, a system called a multi-thread mechanism is used. When a central processor stops operation for a long time upon a reference to a main storage, the multi-thread mechanism interrupts a program currently in execution, and switches the operation to another program. Three types of control systems are used for the multi-thread mechanism: systems called an SMT (Simultaneous Multi Threading), and an HMT (Horizontal Multi Threading) that simultaneously operate two or more programs, and a system called a VMT (Vertical Multi Threading) that usually operates one program, and switches the operation of this program to the operation of another program upon occurrence of a waiting for a main storage.
A central processor that carries out a multi-thread operation shares an operation device, a primary cache memory, a secondary cache memory, and move-in buffers (hereinafter, “MIBs”) for the primary cache and the secondary cache, between threads. It is possible to simultaneously refer to data of the secondary cache and the main storage corresponding to the number of MIBs installed on the central processor. In other words, it is not possible to refer to the data in the secondary cache and the main storage more than the number of the MIBs that are installed on the central processor.
When one thread uses all the MIBs during a multi-thread operation, it is not possible to refer to data of the secondary cache and the main storage when other threads cause a cache miss. After a cache line requested from the MIB returns to the central processor, the cache line is registered into the primary cache or the secondary cache of the central processor. The MIB is released after this registration. The release of the MIB is delayed substantially if a cache line is fetched from the main storage. During this delay period, data of the secondary cache or the main storage cannot be referred to from other threads. Therefore, although multi-thread operation is carried out, a cache miss caused by one thread stops the operation of all the threads. Japanese Patent Application Laid-Open No. 2002-342163 discloses a conventional technique of controlling sharing and non-sharing of a cache among threads during a multi-thread operation.
According to the conventional technique, sharing and non-sharing of a cache among threads can be controlled during a multi-thread operation. However, the Patent Literature 1 does not disclose a conventional technique regarding an MIB to be used for the registration of a cache line to a cache. Therefore, the problem of the stoppage of the operation of all the threads when even one thread causes a cache miss during a multi-thread operation, remains unsolved.